Behavioral modeling of continuous time ∆Σ modulators

A mixed-signal continuous time behavioral model of a continuous time delta-sigma modulator (CT ∆Σ) is presented. CT ∆Σ modulators, by their nature, are mixed-signal systems. That fact creates a discontinuity in the traditional IC design flow which assumes that “discrete” and “continuous” time domain designs require separate design tools. In this work, we present a top level behavioral CT ∆Σ model that can be used within the analog IC design environment. High speed CT ∆Σ modulators are implemented using both “analog” and ”digital“ subblocks. We created mixed-signal models of the subblocks in order to efficiently perform simulations that accurately reflect circuit behavior in the continuous time domain. The models were built out of primitives available in SPICE and Verilog −A . We present a first order CT low-pass ∆Σ (CTLP ∆Σ) as well as a fourth order CT band-pass ∆Σ (CTBP ∆Σ) to demonstrate the modeling technique and simulation methodology. We explored the influence of the loop delay and clock jitter on the CT ∆Σ performance.